This setup seems to work fine for all synths in the studio apart from the Pro 3. The reasoning behind this setup is that it allows us to record midi or audio for each synth in the studio. an audio channel that has it's input set as the output (post mixer) of the midi channel. This is where the bar long midi note is triggered.Ģ. a midi channel with an external instrument plugin, these generally have 7-8ms of latency set. I've tried power cycling with the USB cable plugged in, still can't get it working.Ībleton set up: Delay compensation and reduced latency while monitoring are turned on. I understand there is a bug with USB midi in this version that we're waiting to be resolved. I've tried to get it working with USB midi to sanity check but I can't seem to get it working. Pro 3 has latest firmware installed: 1.1.0. For it to be "in time" it must show each note of the arpeggiator as being on the grid in the resultant audio recording. This is weird.īy "in time" I mean that the audio signal that gets recorded in Ableton is on the grid when I use a basic patch with arpeggiator and trigger it with a bar long midi note from Ableton. The Pro 3 needs an offset of "+1ms" to be set on the ERM in order for it to be in time. There are other synths also clocked by the ERM and all have an offset between +30 to +49 as is to be expected. There is a Prophet 08 also being clocked by the same ERM multiclock at the same time, in order to be in time it's offset is set at +49ms. This means that we would expect any synth clocked by the ERM to need an offset set on the ERM of around +50ms or a little less in order to account for latency. The ERM is sent an audio signal from Ableton as it's master clock, on a track that has a -50ms delay. The Pro 3 is being clocked via midi din from an ERM multiclock. I've looked through the previous posts here and nothing seems to cover it, so I've created a detailed bug report. If its greater than 2ns, manipulate clock skews.Firstly, I love this synth! However I am having some weird sync issues with the Pro 3. Hold timing doesnot depend on clock frequency so lets leave that out. What cycle adjust of 2ns will mean is that, there can only be data path delay of 2ns on this path (assuming zero clock skew) to avoid setup violation. This is less than #1 and hence the correct cycle adjust. Data launched at 18ns and captured at 20ns. This gives 0ns as candidate but its not accepted as cycle adjust, throw this out too.Ĥ. Data launched at 12ns and captured at 12ns. This gives 6ns as candidate but since we already have lesser value from #1, throw it out.ģ. Data launched at 6ns and captured at 12ns. Data launched at 0ns and captured at 4ns. Cycle adjust calculation is what is shown how it is calculated. Its ofcourse not a full clock cycle, neither is it half of 6 ns or 8ns clock. Next, you gotta figure out what the cycle adjust is between the two clocks. The reason that the figure has waveform drawn for 24ns is because the LCM of 6 and 8 is 24. Let's not get all delusional instead lets stick to the given facts. Also, the two clocks are in phase, c'mon see the edges lining up at 0 and then 12ns and again at 24ns. Launch flop is rise edge triggered and capture flop is Falling edge triggered. One thing most people here are confusing is that both the FFs are not positive edge triggered. I think we can still check timing for these two flops. There's a lot of info out there about clock-domain crossing, synchronizers, etc. If the input rate were the slower one then it would be a different story (but still messy). I suggest you either add a FIFO or a multi-cycle constraint. Thus, the output of the B FF after the B rising edge at time 8 will be the SECOND data bit from A the first one never gets clocked into B. But at time 6, NEW data will be clocked out to the D input of B. Using your timing diagram above, after the first A clock edge data will appear at the D input of the B ff. There's no way (that I'm aware of) that you can guaranteed the exact timing of the output of the second ff. However, if this is a critical path then you're going to have to add a synchronizer or FIFO. Is this an FPGA or ASIC design? If so, then depending on the specifics of this circuit you may want to give it a relaxed constraint (like a multi-cycle or ignore). You can't really check this for timing-it's indeterminate (even if you know all the propagation delays, etc) because of the non-integer relationship between the two clocks.
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